Veriflow Cc Agent Skill
VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilog/Yosys) using a stateful, zero-dependency LLM orchestration skill. Features sub-agent nesting for code gen and behavioral-driven verification.
Veriflow Cc is an open-source agent skill by bjwanneng, written mainly in Python, with 55 GitHub stars. Its code was last updated Oct 5, 2026.
Not scanned yet
This listing was imported from public GitHub data and hasn't been through AgenticMart's security scan. Until it is, treat it like any unreviewed code: read the source and limit what it can access.
- Static code scan — pending
- Secrets & dependency CVEs — pending
- Build & boot check — pending
- Network egress audit — pending
- Public report — pending
Veriflow Cc alternatives
View more →Similar agent skills in Design & Media, ranked by GitHub stars. Compare licence, recent activity and scan status before you choose.
| Name | Stars | Licence | Last updated | Scan |
|---|---|---|---|---|
| Veriflow Cc (this page) bjwanneng | 55 | None found | Oct 5, 2026 | Not scanned yet |
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