Verilog Generator Agent Skill
Agent skill for Verilog-2001 RTL generation and FPGA design workflows.
Verilog Generator is an open-source agent skill by Eriemon, written mainly in Python, with 326 GitHub stars and the Apache-2.0 license. Its code was last updated Aug 25, 2026.
Scan summary: scanned Nov 5, 2026 at commit 007372f. Seen able to read environment and secrets. Scan policy
What Verilog Generator can touch
- Our checks did not find this. The tool may still do it.Run shell commandsNot seen in this scan
- Our checks did not find this. The tool may still do it.Run dynamic codeNot seen in this scan
- Our checks did not find this. The tool may still do it.Read or write filesNot seen in this scan
- Seen in this scan, either in the code or while it ran.Read environment and secretsFound in the code by our scan
- Our checks did not find this. The tool may still do it.Control a web browserNot seen in this scan
- Our checks did not find this. The tool may still do it.Connect to databasesNot seen in this scan
- Our checks did not find this. The tool may still do it.Read or send messagesNot seen in this scan
- Our checks did not find this. The tool may still do it.Touch money or tradingNot seen in this scan
- Our checks did not find this. The tool may still do it.Connect to the internetNot run in this scan
"Not seen" means our checks did not find it, and the tool may still do it. Covers commit 007372f, Nov 5, 2026. See the scan policy.
Before you install Verilog Generator
AgenticMart scanned Verilog Generator on Nov 5, 2026 with automated checks for hidden code, known-malicious packages, leaked secrets and vulnerable dependencies. The result covers one commit under our scan policy, so review what access you give it and check any advisories shown here.
What it can access
- A skill is instructions plus optional scripts. The instructions steer your agent; any scripts run on your machine when the agent uses the skill.
Before you install
- Pin the version you reviewed instead of always installing the latest release.
- Read the tool list or scripts before the first run, and keep approval prompts on for actions that write, send or delete.
- Maintained by Eriemon on GitHub, 326 stars and 23 forks. Popularity is not proof of safety.
- Last code change: Aug 25, 2026.
- Open-source license: Apache-2.0.
Verilog Generator is an open-source agent skill by Eriemon, written mainly in Python. Agent skill for Verilog-2001 RTL generation and FPGA design workflows.
At a glance
- Stars
- 326
- Forks
- 23
- Language
- Python
- License
- Apache-2.0
- Created
- May 2026
- Last update
- Aug 25, 2026
- Type
- Agent Skill
- Price
- Free
Topics
Questions about Verilog Generator
What is Verilog Generator?
Agent skill for Verilog-2001 RTL generation and FPGA design workflows.
Who maintains Verilog Generator?
Verilog Generator is maintained by Eriemon on GitHub (Eriemon/verilog-generator). AgenticMart lists it from public repository data.
Is Verilog Generator safe to use?
AgenticMart scanned Verilog Generator on Nov 5, 2026 with automated checks for hidden code, known-malicious packages, leaked secrets and vulnerable dependencies. The result covers one commit under our scan policy, so review what access you give it and check any advisories shown here.
What license does Verilog Generator use?
It is published under the Apache-2.0 license.
Verilog Generator alternatives
View more →Similar agent skills in Productivity & Workflow, ranked by GitHub stars. Compare licence, recent activity and scan status before you choose.
| Name | Stars | Licence | Last updated | Scan |
|---|---|---|---|---|
| Verilog Generator (this page) Eriemon | 326 | Apache-2.0 | Aug 25, 2026 | Scanned, no flagged issues |
| Eigent eigent-ai | 16k | Apache-2.0 | Nov 1, 2026 | Scanned, no flagged issues |
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| Skill anbeime | 9k | None found | Nov 1, 2026 | Not scanned yet |
| Refly refly-ai | 7.5k | None found | Oct 21, 2026 | Not scanned yet |
| N8n Skills czlonkowski | 6.6k | MIT | Oct 24, 2026 | Scanned, no flagged issues |